The present invention relates to a testing system for a logic circuit and, more particularly, to a method and a device for testing a logic circuit such as a logic LSI (which is an abbreviation for Large Scale Integration) circuit.
In general, a logic LSI circuit comprises a plurality of flip-flops and a combination circuit including AND gates, OR gates, inverters or the like. In recent years, in order to easily execute a test for such a logic circuit, a scanning system has been suggested. In the scanning system, the flip-flops are arranged in parallel so that the flip-flops serve as registers. A signal path, which is called a scanning path, is formed between scanning-in and scanning-out terminals of the circuit. The scanning path is connected to one of the flip-flops by an addressing means. Therefore, the scanning path can be connected to each of the flip-flops in an ordered sequence by the addressing means.
Testing of such a logic circuit is executed separately for the flip-flops and the combination circuit. Among them, testing of the flip-flops is executed by supplying input data from the scanning-in terminal to one of the flip-flops, obtaining output data therefrom at the scanning-out terminal and checking whether or not the output data is the same as the input data. This is a simple operation. In contrast, testing of the combination circuit is a complex operation.
In the prior art, the combination of a logic circuit is tested by using the flip-flops thereof which have already been tested. First, input test data is set in sequence in the flip-flops of the logic circuit by a testing device. After that, the combination circuit executes a logic operation upon the data stored in the flip-flops and the result thereof is again stored in the flip-flops. Next, the results are provided as output data, in sequence, from the flip-flops to the testing device. After that, in the testing device, the output data is compared with predetermined data and testing of the combination circuit is completed.
However, in the above-mentioned prior art system, in order to set the input data in the flip-flops, a large number of input test patterns, each of which includes an address code designating one of the flip-flops, input data, a clock code or the like, are required. Similarly, in order to obtain the operation result from the flip-flops, a large number of output test patterns, each of which also include an address code designating one of the flip-flops, output data, and a clock code or the like, are required. In this case, the number of input test patterns or output test patterns are the same as the number of flip-flops. As a result, the capacity of memory devices, such as magnetic tapes, for storing the test patterns must be large. In addition, the number of transmissions of test patterns between the testing device and the logic circuit must be large, so that the test executing time becomes long.